In one type of circuit element or device, hereinafter "tunneling device," electrons are caused to "tunnel" from a first conductor to a second conductor through an insulating dielectric separating the first and second conductors from each other. This effect is termed the Fowler-Nordheim field emission of electrons. This field emission of electrons occurs in response to a voltage difference across the dielectric by means of the application of different voltages to each conductor. When this voltage difference exceeds a threshold voltage, the Fowler-Nordheim field emission or tunneling of electrons is induced in the dielectric.
The tunneling device constitutes an unknown impedance to the applied voltage. When the voltage applied is less than the tunneling device's threshold voltage, the device acts primarily as a capacitive impedance, with charge accumulating on each conductor as the voltage increases across the dielectric. However, when the tunneling threshold voltage is exceeded, the tunneling of electrons occurs and current flows through the dielectric. Thus, above the tunneling threshold voltage, the input impedance of the tunneling device also has a resistive component.
An electrically erasable, programmable read only memory (EEPROM) and a nonvolatile random access memory (NOVRAM) are examples of integrated circuits which have tunneling devices. In each of these memories, there is a plurality of nonvolatile memory cells. In each cell, a polysilicon floating gate is totally surrounded by a dielectric, so that the charge state of the floating gate remains undisturbed for very long periods of time in the absence of voltages high enough to cause tunneling to occur. The charge level on the floating gate, i.e., the presence or absence of excess electrons, is used to represent a binary data state in the cell. Charge is applied to and removed from the floating gate through a programming tunneling region and an erase tunneling region, respectively, which are formed in the dielectric surrounding the floating gate. The position of each of these tunneling regions may be defined by a polysilicon layer which is positioned such that it overlaps a portion of the floating gate and is spaced from the floating gate a selected distance by the dielectric formed therebetween. See, for example, U.S. Pat. No. 4,274,012.
In one embodiment of the floating gate cell, electrons are introduced onto the floating gate, in a "programming" mode as follows. A low potential is applied to a programming electrode disposed adjacent to the dielectric forming the programming tunneling region and capacitively coupled to the floating gate. A high potential is applied to a bias electrode. The bias electrode is capacitively coupled to the floating gate such that the potential of the floating gate is elevated to the high potential. Therefore, a potential difference exists across the programming tunneling region. The applied low and high potentials are selected so that this potential difference exceeds the tunneling threshold of the dielectric in the programming region so that electrons are introduced by tunneling onto the floating gate.
Similarly, electrons are removed from the floating gate, in a "erase" mode, as follows. An erase electrode is disposed adjacent to the erase tunneling region and capacitively coupled to the floating gate. A low potential is applied to a bias electrode such that the floating gate is capacitively coupled to the low potential. Upon application of a sufficiently high potential to the erase electrode, a potential difference is developed across the dielectric in the erase tunneling region which exceeds the tunneling threshold voltage. Electrons are then removed from the floating gate by tunneling to the erase electrode.
An important feature of state of the art EEPROMS and NOVRAMS is that they be operable from a single external low voltage supply (e.g., 5 volts). Consequently, the high potentials or voltages necessary to program or erase a floating gate cell in such a memory must be generated using on-chip circuitry. This single external supply feature makes such memories much easier to use in most applications. However, generating the high voltages necessary for the nonvolatile program and erase operations using one or more on-chip high voltage generators greatly limits the amount of current that can be supplied to the non-volatile memory cell compared to the current that would be available if an external high voltage supply provided the high voltage power source. This is because a charge pump of reasonable size formed on the memory chip can only supply typically 10 to 40 microamps, whereas an external high voltage power source can easily supply several milliamps or more. Consequently, it is important for the operation of such on-chip power supplies to make sure that the various circuits which use the on-chip high voltages draw the minimum amount of current necessary for operation. If any such circuit were to draw a current in excess of a few tens of microamps, that circuit would pull down the high voltage charge pump output voltage, preventing the high voltage power source from attaining the voltage necessary to cause tunneling to occur and to successfully complete a nonvolatile write operation.
One prior art method for eliminating the problem of defective cells which excessively load down on-chip high voltage generators is to incorporate on-chip redundancy. Such redundancy also increases yield and reduces costs in large EEPROM chips. By adding a few extra rows or columns to the array and adding special circuitry in the decoder, a defective bit or row or column can be replaced during testing of the chip with a good redundant row or column to make a fully functional part. It is particularly convenient and inexpensive to adapt redundancy to an EEPROM since EEPROM cells can be used to permanently retain the addresses of the defective rows or columns that are being replaced by good redundant rows or columns.
However, if the memory device includes a mass program or mass erase capability, all of the rows in the array including the redundant rows and the rows containing defective cells are coupled to the on-chip high voltage generator during such an operation. The mass mode capability is an important functionality for a memory device since it significantly reduces the time required to test the memory device as the entire array of cells can be erased or programmed in one high voltage store operation, which typically takes about 5 or 10 milliseconds. This is in contrast to the several seconds it takes to write a large EEPROM in a page write mode where each page takes about 5 to 10 milliseconds to write and where, for example, there are 256 or 512 pages. The mass mode feature is also useful in applications where data security is important and the user needs to quickly remove all of the data in the EEPROM. Thus, it is even more important in such a memory device that means be provided for coupling the high voltage to each cell in a manner in which the current to each row line is limited or controlled to prevent a shorted or leaky cell from holding down the high voltage generator. However, to avoid current limiting to good cells, since it is not needed or desirable, a high voltage coupler having a dual mode is needed to limit current to rows with defective bits but not to rows that operate normally.